Switching regulator is a small, lightweight, high-efficiency DC power supply using semiconductor switching elements, and is in wide use in electronic devices, etc. In recent years, the demand for smaller size, lighter weight and higher efficiency has constantly increased. The basic principle of the switching regulator is as follows: the switching elements are turned on/off at a high frequency, and the ratio of the on/off periods, that is, the duty ratio, is controlled so that the DC output voltage is kept at a constant level. So-called non-insolated or chopper type switching regulators are of the following three types: the voltage boost type that can provide higher output voltage than the input voltage, the voltage reducing type that can provide a lower output voltage than the input voltage, and a voltage buck-boost that can provide a constant output voltage independent of the input voltage.
In recent years, the battery application voltage range of portable electronic devices has become wider. Applications of floating capacitance have increased for the type of device that can provide a 3 V nominal power supply voltage to the load while the battery voltage changes from 4 V in the fully charged state to 2.5 V. For this type of application, it is preferred that the voltage buck-boost switching regulator that operates as both voltage boosting type and voltage reducing type be adopted.
FIG. 14 is a diagram illustrating the circuit constitution of a typical voltage buck-boost switching regulator of the prior art.
This voltage buck-boost switching regulator is composed of a pair of voltage reducing transistors M1, M2, a pair of voltage boosting transistors M3, M4, inductance coil 100, output capacitor Co, and controller 102.
More specifically, the two terminals of inductance coil 100 are connected to nodes Na, Nb. Here, NMOS transistor M1 is connected between reference voltage terminal (Vss) at ground potential and node Na. PMOS transistor M2 is connected between voltage input terminal 104 and node Na. Also, NMOS transistor M3 is connected between reference voltage terminal (Vss) at ground potential and node Nb, and PMOS transistor M4 is connected between voltage output terminal 105 and node Nb. Output capacitor Co is connected between voltage output terminal 105 and reference voltage terminal (Vss) at ground potential. For example, voltage input terminal 104 is connected to primary battery or secondary battery (not shown in the figure), and voltage output terminal 105 is connected to any load circuit (not shown in the figure).
Under the control of controller 102, when the voltage reducing operation is performed, voltage boosting transistors M3, M4 are kept in a steady state pass node with respect to voltage output terminal 105, that is, PMOS transistor M4 is turned on, NMOS transistor M3 is turned off, and voltage reducing transistors M1, M2 are turned on/off with a variable duty ratio. When the voltage boosting operation is performed, voltage reducing transistors M1, M2 are kept in the steady state through state with respect to voltage input terminal 104, that is, PMOS transistor M2 is turned on, NMOS transistor M1 is turned off, and voltage boosting transistors M3, M4 are turned on/off with a variable duty ratio for the various switching cycles.
Said controller 102 has voltage feedback circuit 106 that feeds back output voltage Vo from voltage output terminal 105 to generate error voltage Verr, and comparison reference wave signal circuit 108 that generates a voltage reducing sawtooth wave signal Vrp1 and voltage boosting sawtooth wave signal Vrp2 with respect to error voltage Verr.
Said voltage feedback circuit 106 operates as follows: output voltage Vo is divided by a constant ratio by voltage dividing resistors 110, 112; divided voltage Vfb is compared with reference voltage Vref by means of error amplifier 114 made of an op amp, and the difference is amplified at a constant amplification rate to generate error voltage Verr. Here, phase compensation circuit 116 for adjusting the frequency transfer function (response characteristics) of the voltage feedback loop is connected to error amplifier 114. Said phase compensation circuit 116 is composed of three capacitors 118, 120, 122 and three resistors 124, 126, 128.
Said comparison reference wave signal circuit 108 consists of the following parts: oscillator 130 that oscillates and outputs clock signal CK at a constant frequency, sawtooth wave generator 132 that generates first sawtooth wave signal Vrp1 synchronized with clock signal CK and having a constant slope and a constant amplitude, and level transforming circuit 134 that increases the voltage level of first sawtooth wave signal Vrp1 by a constant amount corresponding to said amplitude to form second sawtooth wave signal Vrp2.
In addition, controller 102 has the following parts: first comparator 136, which compares error voltage Verr with first sawtooth wave signal Vrp1, and, corresponding to the relationship between them with respect to magnitude, outputs a binary signal as voltage reducing PWM (pulse width modulation) switching signal Ppwm1, and voltage reducing driver 138 that performs switching driving for voltage reducing transistors M1, M2 corresponding to voltage reducing PWM switching signal Vpwn1. Also, there are the following parts: second comparator 140, which compares error voltage Verr with second sawtooth wave signal Vrp2, and, corresponding to the relationship between them in magnitude, outputs a binary signal as voltage boosting PWM switching signal Vpwm2, and voltage boosting driver 142, which performs switching driving for voltage boosting transistors M3, M4 corresponding to voltage boosting PWM switching signal Vpwm2.
FIG. 15 is a waveform diagram illustrating the operation of said voltage buck-boost switching regulator.
When input voltage Vi is higher than output voltage Vo, that is, in the voltage reducing mode, the level of error voltage Verr output from error amplifier 114 is relatively low, and, in each switching cycle defined at clock signal CK, error voltage Verr crosses only first sawtooth wave signal Vrp1 and does not cross second sawtooth wave signal Vrp2.
In this case, during the former period, from the start of each switching cycle to the time when error voltage Verr crosses first sawtooth wave signal Vrp1, Verr>Vrp1, the output of first comparator 136, that is, PWM switching signal Vpwm1, is at the H level, and voltage reducing transistors M1, M2 are in the off and on states, respectively. Then, during the latter period, from the time when error voltage Verr crosses first sawtooth wave signal Vrp1 to end of said switching cycle, Verr<Vrp1, PWM switching signal Vpwm1 is at the L level, and voltage reducing transistors M1, M2 are in the on and off states, respectively. On the other hand, the output of second comparator 140, that is, voltage boosting PWM switching signal Vpwm2 is at the H level throughout the entire period of the switching cycle, and voltage boosting transistors M3, M4 are kept in the off and on states, respectively.
As said input voltage Vi falls, the level of error voltage Verr rises under feedback control, and the proportion of the on time of transistor M2 during each switching cycle, that is, the duty ratio, rises. Here, the level of error voltage Verr does not cross first sawtooth wave signal Vrp1, and the voltage reducing operation stops. As a result, it crosses second sawtooth wave signal Vrp2, and the voltage boosting operation is performed.
In the voltage boosting operating mode, during the former period, from the start of each switching cycle to the time when error voltage Verr crosses second sawtooth wave signal Vrp2, Verr>Vrp2, the output of second comparator 140, that is, voltage boosting PWM switching signal Vpwm2 is at the L level, and voltage boosting transistors M3, M4 are in the on and off states, respectively. Then, during the latter period, from the time when error voltage Verr crosses second sawtooth wave signal Vrp2 to the end of said switching cycle, Verr<Vrp1, voltage boosting PWM switching signal Vpwm2 is at the H level, and voltage boosting transistors M3, M4 are in the off and on states, respectively. On the other hand, the output of first comparator 136, that is, PWM switching signal Vpwm1 is at the H level throughout the entire period of the switching cycle, and voltage boosting transistors M1, M2 are kept in the on and off states, respectively. During the voltage boosting operation, as input voltage Vi falls, under feedback control, the level of error voltage Verr rises, and the on time of transistor M3 during each switching cycle, that is, the duty ratio, increases.
In recent years, there has been greater demand for the voltage buck-boost switching regulators for electronic devices that operate at the power supply voltage obtained by means of DC-DC conversion from Li ion batteries or other secondary batteries. On the other hand, as the application voltage range of said secondary batteries becomes wider, there is a demand for a type of voltage buck-boost switching regulator with stable, high-speed response characteristics and output characteristics that can also handle a high current load. Also, for the voltage buck-boost switching regulator, when the voltage boosting operation is performed, unlike the voltage reducing operation, in the frequency characteristics of the constant-voltage feedback loop, there is a 180° phase log in the frequency characteristics. Consequently, compared with the voltage reducing operation, the operation tends to become more unstable, and a solution is required.
In order to meet said demand, for said voltage buck-boost switching regulator (FIG. 14), the circuit constitution and selection of constants of phase compensation circuit 116 are designed to solve said problems. In the example shown in the figure, phase compensation circuit 116 has three capacitors 118, 120, 122 and three resistors 124, 126, 128, and the voltage feedback circuit is formed with two zeroes and two poles in the frequency transfer characteristics.
However, because the number of circuit elements of phase compensation circuit 116 is increased, not only does the cost increase, but also the order of the frequency transfer function increases, and it becomes quite difficult to set the optimum constants in phase compensation circuit 116 to ensure stable operation over the entire region of the wide output voltage range from voltage reducing to voltage boosting. In order to solve the aforementioned problem, a scheme has been proposed in which individual phase compensation circuits are arranged for the voltage reducing operation and the voltage boosting operation, respectively, so that the constants can be easily set for the individual phase compensation circuits, respectively. However, according to this scheme, the number of the plural phase compensation circuits is increased, so that the circuit scale becomes even larger, and the size and cost of the semiconductor chip becomes much larger, which is undesirable.